M16C6N4 Datasheet, PDF (396/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6N4) Hardware Manual
Rev. Date
2.00 Nov. 10, 2004
Page
38
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Description
Summary
Table 7.1 Difference between Separate Bus and Multiplexed Bus is added.
Figure 7.1 CSR Register: NOTE 2 is revised.
Table 7.8 Software Wait Related Bits and Bus Cycles
• Bus Cycle of SFR (PM20 = 0) is revised from "2 BCLK cycles" to "3 BCLK cycles".
• Bus Cycle of SFR (PM20 = 1) is revised from "3 BCLK cycles" to "2 BCLK cycles".
• From bottom to 5th item in CSR Register: The value is revised from "1" to "0".
• NOTE 5 is added.
Table 8.1 Clock Generating Circuit Specifications
• Clock Frequency in PLL Frequency Synthesizer: 16 MHz is added.
Figure 8.1 Clock Generating Circuit: Block diagram (upper) is revised.
Figure 8.2 CM0 Register
• Bit name of CM02 is revised.
• NOTE 6 (2) and NOTE 8 are revised.
Figure 8.3 CM1 Register: NOTE 3 of CM11 bit is deleted.
Figure 8.6 CCLKR Register: Location of NOTE 2 is changed and NOTE 3 is added.
Figure 8.7 PM2 Register: NOTE 2 is revised.
Figure 8.8 PLC0 Register: Function of 011b and 100b in PLC02 to PLC00 bits are revised
from "Multiply by 6 and Multiply by 8" to "Do not set a value".
8.1.4 PLL Clock 11th line: 16 MHz is added to PLL clock frequency.
Table 8.2 Example for Setting PLL Clock Frequencies
• PLL clock = 16 MHz is added. (8✕2, 4✕4)
• 16 MHz is added to NOTE 1.
Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source
• 4th frame: “(To select a 16 MHz or higher PLL clock)” is revised to “(When PLL clock
>16 MHz)”.
8.4.1.2 PLL Operation Mode: 1st line
• The main clock multiplied is revised from "by 2, 4, 6 or 8" to "by 2 or 4".
Table 8.3 Setting Clock Related Bit and Modes
• CM21 bit in Low Power Dissipation Mode: Value is revised from "-" to "0".
• CM11 bit in Low-Speed Mode, Low Power Dissipation Mode, On-chip Oscillator Mode
and On-chip Oscillator Low Power Dissipation Mode: Value is revised from "-" to "0".
8.4.2 Wait Mode 4th line: "PLL clock" is deleted.
Table 8.4 Pin Status During Wait Mode
• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from
"H" to "L".
Table 8.5 Interrupts to Exit Wait Mode
• CAN0/1 Wake-up Interrupt: "in CAN sleep mode" is added.
8.4.3 Stop Mode
• CAN0/1 Wake-up interrupt: "(when CAN sleep mode is selected)" is added.
Table 8.6 Pin Status in Stop Mode
• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from
" H" to "indeterminate".
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