M16C6N4 Datasheet, PDF (397/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6N4) Hardware Manual
Rev. Date
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2.00 Nov. 10, 2004 67
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Description
Summary
Figure 8.12 State Transition to Stop Mode and Wait Mode
• Figure is revised.
• NOTE 3 is revised.
Figure 8.13 State Transition in Normal Operation Mode
• Low-Speed and Low Power Dissipation Mode: "CM7 = 1” is revised to "CM7 = 0" (3 places).
• NOTES 2, 6 are revised.
Figure 8.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock
is revised.
Table 10.2 Relocatable Vector Tables
• Interrupt Source: "Software interrupt" is revised to "INT Instruction Interrupt"
• NOTES 10, 11 are added.
Figure 10.3 Interrupt Control Registers (1): NOTES 5, 6, 7 are added.
Figure 10.4 Interrupt Control Registers (2)
• NOTE 2 is added to C1RECIC/INT5IC, C1TRMIC/S3IC/INT4IC
• NOTES 6, 7 are added.
Figure 10.11 (upper) IFSR0 Register: NOTE 3 is added.
10.9 CAN0/1 Wake-up Interrupt is revised.
Figure 10.13 CAN0/1 Wake-up Interrupt Block Diagram is revised.
____________
Figure 11.1 Watchdog Timer Block Diagram: "RESET" is revised to "Internal RESET signal".
Figure 13.6 (upper and middle) ONSF Register, TRGSR Register: NOTE 2 is added.
Table 13.1 Specifications in Timer Mode
• Specification of Divide Ratio: "TAiMR register" is revised to "TAi register".
• Specification of Select Function: "When not counting, the pin outputs a low" is
revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".
Table 13.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
• Specification in Select Function: "When not counting, the pin outputs a low" is
revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".
13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing 4th line
________
• "the INT2 pin" is revised to "the ZP pin".
Figure 13.10 Two-phase Pulse (A phase and B phase) and Z Phase
________
• "INT2 (Z phase)" is revised to "ZP".
Figure 13.12 TA0MR to TA4MR Registers in PWM Mode
• Bit name and Function in MR0 bit is revised from "Set to "1" in PWM mode" to "Pulse
Output Function Select Bit ⁽³⁾".
• NOTE 3 is added.
Table 13.6 Specifications in Timer Mode
• Specification in Divide Ratio: "TBiMR register" is revised to "TBi register".
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.
Figure 14.2 INVC0 Register is revised.
Figure 14.3 INVC1 Register: Function of INV13 bit is revised.
Figure 14.4 (upper) IDB0 and IDB1 Registers: (b7-b6) is revised.
Figure 14.4 (lower) DTT Register: NOTE 2 is revised.
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