M16C6N4 Datasheet, PDF (105/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
10. Interrupt
Priority level of each interrupt
INT1
Level 0
(initial value)
Timer B2
Timer B0
Timer A3
Timer A1
UART1 Reception, ACK1
UART0 Reception, ACK0
UART2 Reception, ACK2
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer A0
UART1 Transmission, NACK1
UART0 Transmission, NACK0
A/D Conversion, Key Input
DMA1
UART2 Bus Collision Detection
CAN1 Successful Reception, INT5
Timer B4, UART1 Bus Collision Detection
INT3
CAN0 Successful Reception
UART2 Transmission, NACK2
CAN0/1 Error
DMA0
SI/O3, CAN1 Successful Transmission, INT4
Timer B3, UART0 Bus Collision Detection
Timer B5
CAN0 Successful Transmission
CAN0/1 Wake-up
IPL
I Flag
Address Match
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
DBC
NMI
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock generating circuit
(Figure 8.1 Clock Generating Circuit)
Interrupt request accepted
Figure 10.10 Interrupts Priority Select Circuit
Rev.2.30 Oct 24, 2005 page 87 of 376
REJ09B0009-0230