M16C6N4 Datasheet, PDF (143/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
13. Timers
13.2.1 Timer Mode
In timer mode, the timer counts a count source generated internally.
Table 13.6 lists specifications in timer mode. Figure 13.18 shows TBiMR register in timer mode.
Table 13.6 Specifications in Timer Mode
Item
Specification
Count Source
f1, f2, f8, f32, fC32
Count Operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide Ratio
Count Start Condition
1/(n+1) n: set value of the TBi register 0000h to FFFFh
Set the TBiS bit ⁽¹⁾ to “1” (start counting)
Count Stop Condition Set the TBiS bit to “0” (stop counting)
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
I/O port
Read from Timer
Count value can be read by reading the TBi register
Write to Timer
• When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
Bit Symbol
Bit Name
Function
RW
TMOD0
b1 b0
RW
Operation Mode Select Bit 0 0 : Timer mode
TMOD1
RW
MR0
Has no effect in timer mode
RW
MR1
Can be set to "0" or "1"
RW
TB0MR, TB3MR registers
Set to "0" in timer mode
RW
MR2
TB1MR, TB2MR, TB4MR, TB5MR register s
Nothing is assigned. When write, set to "0".
-
When read, its content is indeterminate.
MR3
When write in timer mode, set to "0".
When read in timer mode, its content is indeterminate.
RO
TCK0
b7 b6
0 0 : f1 or f2
RW
Count Source Select Bit ^{0 1 : f8}
TCK1
1 0 : f32
1 1 : fC32
RW
Figure 13.18 TB0MR to TB5MR Registers in Timer Mode
Rev.2.30 Oct 24, 2005 page 125 of 376
REJ09B0009-0230