M16C6N4 Datasheet, PDF (403/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6N4) Hardware Manual
Rev. Date
2.30 Oct. 24, 2005
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Description
Summary
10.5.8 Returning from an Interrupt Routine: Last sentence (Register bank ...) is added.
10.5.9 Interrupt Priority: First sentence (If two or more...) is revised.
10.5.10 Interrupt Priority Resolution Circuit: First sentence (The interrupt priority level ...)
is revised.
Figure 10.11 IFSR1 Register (upper)
• IFSR17: NOTE 2 is added to Bit Name.
• NOTE 2 is revised.
Table 12.1 DMAC Specifications: DMA transfer Cycles is added.
12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.4.
Figure 13.12 TA0MR to TA4MR Registers in PWM Mode: b2 is revised from “1” to “(blank)”.
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.
Figure 14.2 INVC0 Register: NOTES 5 and 6 are revised.
Figure 15.5 U0BRG to U2BRG Registers (lower): NOTE 3 is added.
Figure 15.6 U0C0 to U2C0 Registers (lower): NOTE 5 is added.
Table 15.9 Example of Bit Rates and Settings: 24 MHz and NOTE 1 is added.
Figure 15.37 S3C Register (upper): NOTE 5 is added.
Figure 15.37 S3BRG Register (middle): NOTE 3 is added.
Table 16.1 A/D Converter Performance
• Performance of Integral Nonlinearity Error: “When AVCC = VREF = 3.3 V” is added.
Figure 16.1 A/D Converter Block Diagram
• ADGSEL1 to ADGSEL0 (righit/lower) is revised from “10b” to “11b”.
16.2.6 Output Impedance of Sensor under A/D Conversion
• 10th line: f(XIN) is revised to f(φAD).
Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit
• fAD is revised to φAD.
Figure 17.1 D/A Convertoer Block Diagram is revised.
Figure 17.2 DA0 and DA1 Registers: Setting Range is added.
Figure 17.3 D/A Converter Equivalent Circuit: NOTE 2 is added.
Figure 18.3 CRC Calculation: Details of CRC operation is revised.
Figure 19.11 C0TECR, C1TECR Registers (2nd register): NOTE 1 is added.
Table 19.2 Examples of Bit-rate: 24 MHz and NOTE 2 is added.
Figure 20.9 PUR1 Register (middle): Value of After Reset is revised.
Figure 21.1 Flash Memory Block Diagram is revised.
Figure 21.2 ROMCP Register is revised.
Table 21.3 EW0 Mode and EW1 Mode: NOTE 1 is revised.
21.3.2 EW1 Mode: Last sentence (When an erase/program ...) is added.
21.3.3.4 FMSTP Bit
• 8th line: Procedure to change the FMSTP bit setting (1) to (4) are added.
Figure 21.7 Processing Before and After Low Power Dissipation Mode or On-chipOscillator
Low Power Dissipation Mode
• Title, First and second frames (left) and top of right: “on-chip oscillator low power
dissipation mode” is addded.
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