M16C6N4 Datasheet, PDF (359/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
22. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
VCC = 3.3V
Read timing
tcyc
BCLK
CSi
td(BCLK-CS)
40ns.max
ADi
/DBi
ADi
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
th(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
Address
td(BCLK-AD)
40ns.max
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
tac3(RD-DB)
(2.5 ✕ tcyc-60)ns.max
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
ALE
th(RD-CS)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-CS)
6ns.min
Data input
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(BCLK-AD)
4ns.min
th(RD-AD)
(0.5 ✕ tcyc-10)ns.min
RD
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
Write timing
tcyc
BCLK
CSi
ADi
/DBi
td(BCLK-CS)
40ns.max
Address
td(BCLK-DB)
50ns.max
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
td(BCLK-AD)
40ns.max
ADi
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
ALE
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
Data output
td(DB-WR)
(2.5 ✕ tcyc-50)ns.min
WR, WRL
WRH
td(BCLK-WR)
40ns.max
tcyc = ¹
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
th(WR-CS)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-CS)
4ns.min
th(BCLK-DB)
4ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-WR)
0ns.min
Figure 22.31 Timing Diagram (8)
Rev.2.30 Oct 24, 2005 page 341 of 376
REJ09B0009-0230