M16C6N4 Datasheet, PDF (106/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
10. Interrupt
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10.6 INT Interrupt
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INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR10 to IFSR15 bits in the IFSR1 register.
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INT4 share the interrupt vector and interrupt control register with CAN1 successful transmission and SI/O3.
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INT5 share the interrupt vector and interrupt control register with CAN1 successful reception. To use the
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INT4 interrupt, set the IFSR16 bit of the IFSR1 register to “1” (INT4). To use the INT5 interrupt, set the
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IFSR17 bit of the IFSR1 register to “1” (INT5).
After modifying the IFSR16 or IFSR17 bit, set the corresponding IR bit to “0” (interrupt not requested)
before enabling the interrupt.
Figure 10.11 shows the IFSR0 and IFSR1 registers.
Rev.2.30 Oct 24, 2005 page 88 of 376
REJ09B0009-0230