M16C6N4 Datasheet, PDF (32/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
3. Memory
3. Memory
Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6N4). The address space extends the 1
Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be
used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
00000h
SFR
00400h
XXXXXh
0F000h
0FFFFh
10000h
Internal RAM
Reserved area ⁽¹⁾
Internal ROM
(data area) ⁽³⁾
External area
FFE00h
Special page
vector table
Internal RAM
Capacity Address XXXXXh
5 Kbytes
017FFh
10 Kbytes
02BFFh
Internal ROM ⁽³⁾
Capacity Address YYYYYh
128 Kbytes
E0000h
256 Kbytes
C0000h
27000h
28000h
80000h
YYYYYh
FFFFFh
Reserved area
External area
Reserved area ⁽²⁾
Internal ROM
(program area) ⁽⁴⁾
FFFDCh
FFFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop and re-oscillation
detection / watchdog timer
DBC
NMI
Reset
NOTES:
1. During memory expansion mode or microprocessor mode, cannot be used.
2. In memory expansion mode, cannot be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. When using the masked ROM version, write nothing to internal ROM area.
5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" (block A enabled, addresses 10000h to
26FFFh for CS2 area) and the PM13 bit in the PM1 register is "1" (internal RAM area is expanded over 192 Kbytes).
Figure 3.1 Memory Map
Rev.2.30 Oct 24, 2005 page 14 of 376
REJ09B0009-0230