M16C6N4 Datasheet, PDF (107/406 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6N4)
10. Interrupt
Interrupt Request Cause Select Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR0
Address
01DEh
After Reset
00XXX000h
Bit Symbol
IFSR00
Bit Name
Interrupt Request Cause
Select Bit
Function
RW
0 : CAN1 successful transission
1 : SI/O3
RW
IFSR01
Interrupt Request Cause
Select Bit
0 : A/D conversion
1 : Key input
RW
IFSR02
Interrupt Request Cause
Select Bit ⁽³⁾
0 : CAN0/1 wake-up or error
1 : CAN0 wake-up/error or
RW
CAN1 wake-up/error
-
(b5-b3)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
RW
IFSR06
Interrupt Request Cause
Select Bit ⁽¹⁾
0 : Timer B3
1 : UART0 bus collision detection
RW
IFSR07
Interrupt Request Cause
Select Bit ⁽²⁾
0 : Timer B4
1 : UART1 bus collision detection
RW
NOTES:
1.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
When using the timer B3 interrupt, set the IFSR06 bit to "0" (Tmer B3).
When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection).
2.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4 interrupt, set the IFSR07 bit to "0" (Timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection).
3.If this bit is set to "0", the software interrupt number 1 is selected CAN0/1 wake-up and the interrupt
number 13 is selected CAN0/1 error. If this bit is set to "1", the interrupt number 1 is selected CAN0
wake-up/error and the interrupt number 13 is selected CAN1 wake-up/error.
Interrupt Request Cause Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR1
Address
01DFh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
IFSR10
INT0 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR11
INT1 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR12
INT2 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR13
INT3 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR14
INT4 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR15
INT5 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR16
Interrupt Request Cause
Select Bit ⁽²⁾
0 : SI/O3/CAN1 successful transmission ⁽³⁾
1 : INT4
RW
IFSR17
Interrupt Request Cause
Select Bit ⁽²⁾
0 : CAN1 successful reception
1 : INT5
RW
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT0IC to INT5IC register is set
to "0" (falling edge).
2.During memory expansion and microprocessor modes, when the data bus is 16-bit width (BYTE pin is
"L"), set this bit to "0".
3.When setting this bit to "0" (SI/O3, CAN1 successful transmission), make sure the IFSR00 bit in the
IFSR0 register is set to "0" (CAN1 successful transmission) or "1" (SI/O3).
And, make sure the POL bit in the S3IC and C1TRMIC registers are set to "0" (falling edge).
Figure 10.11 IFSR0, IFSR1 Registers
Rev.2.30 Oct 24, 2005 page 89 of 376
REJ09B0009-0230