HD64F3664FPV Datasheet, PDF (99/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Address Break
Bit
Bit Name
1
DCMP1
0
DCMP0
[Legend]
X: Don't care.
Initial
Value R/W
0
R/W
0
R/W
Description
Data Compare Condition Select 1 and 0
These bits set the comparison condition between the
data set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and
data bus
11: Compares 16-bit data between BDR and data bus
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 19.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
Word Access
Even Address Odd Address
ROM space
Upper 8 bits
Lower 8 bits
RAM space
Upper 8 bits
Lower 8 bits
I/O register with 8-bit Upper 8 bits
data bus width
Upper 8 bits
I/O register with 16- Upper 8 bits
bit data bus width
Lower 8 bits
Byte Access
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
—
—
Rev. 6.00 Mar. 24, 2006 Page 69 of 412
REJ09B0142-0600