HD64F3664FPV Datasheet, PDF (278/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
15.3.7 Timer Serial Control Register (TSCR)
The timer serial control register (TSCR) is an 8-bit readable/writable register that controls the
operating modes.
Bit
7 to 2
1
0
Bit Name
−
Initial
Value
All 1
IICRST 0
IICX
0
R/W Description
−
Reserved
This bit is always read as 1 and cannot be modified.
R/W I²C Control Unit Reset
Resets the control unit except for the I²C registers.
When a hang up occurs due to illegal communication
during I²C operation, setting IICRST to 1 can set a port
or reset the I²C control unit without initializing registers.
R/W I²C Transfer Rate Select
Selects the transfer rate in master mode, together with
bits CKS2 to CKS0 in ICMR. Refer to table 15.3.
When, with the I²C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal
flag is set, the readable IRTR flag may or may not be set. Even when the IRIC flag and IRTR flag
are set, the TDRE or RDRF internal flag may not be set. Table 15.4 shows the relationship
between the flags and the transfer states.
Rev. 6.00 Mar. 24, 2006 Page 248 of 412
REJ09B0142-0600