HD64F3664FPV Datasheet, PDF (115/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
3
NESEL
0
R/W Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ ) and the system clock pulse generator
W
generates the oscillator clock (φ ). This bit selects the
OSC
sampling frequency of the oscillator clock when the
watch clock signal (φ_W) is sampled. When φ_OSC = 4 to 16
MHz, clear NESEL to 0.
2

0: Sampling rate is φ_OSC/16
1: Sampling rate is φ /4
OSC
0

Reserved
1

0

These bits are always read as 0.
0

0

Table 6.1 Operating Frequency and Waiting Time
STS2 STS1 STS0 Waiting Time
0
0
0
8,192 states
1
16,384 states
1
0
32,768 states
1
65,536 states
1
0
0
131,072 states
1
1,024 states
1
0
128 states
1
16 states
Note: Time unit is ms.
16 MHz 10 MHz 8 MHz
0.5
0.8
1.0
1.0
1.6
2.0
2.0
3.3
4.1
4.1
6.6
8.2
8.2
13.1 16.4
0.06 0.10 0.13
0.00 0.01 0.02
0.00 0.00 0.00
4 MHz
2.0
4.1
8.2
16.4
32.8
0.26
0.03
0.00
2 MHz
4.1
8.2
16.4
32.8
65.5
0.51
0.06
0.01
1 MHz
8.1
16.4
32.8
65.5
131.1
1.02
0.13
0.02
0.5 MHz
16.4
32.8
65.5
131.1
262.1
2.05
0.26
0.03
Rev. 6.00 Mar. 24, 2006 Page 85 of 412
REJ09B0142-0600