HD64F3664FPV Datasheet, PDF (129/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 ROM
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit
7 to 5
Bit
Initial
Name Value R/W
—
All 0
—
4
EB4
0
R/W
3
EB3
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
0
EB0
0
R/W
Description
Reserved
These bits are always read as 0.
When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
will be erased.
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
will be erased.
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit
Initial
Bit
Name Value R/W
7
PDWND 0
R/W
6 to 0 —
All 0
—
Description
Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to
subactive mode.
Reserved
These bits are always read as 0.
Rev. 6.00 Mar. 24, 2006 Page 99 of 412
REJ09B0142-0600