HD64F3664FPV Datasheet, PDF (200/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer W
Initial
Bit
Bit Name Value
1
IOC1
0
0
IOC0
0
[Legend]
X: Don't care.
R/W Description
R/W I/O Control C1 and C0
R/W When IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC
pin
01: Input capture to GRC at falling edge of the FTIOC
pin
1X: Input capture to GRC at rising and falling edges of
the FTIOC pin
12.3.7 Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to
CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting
the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF
flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is
generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
TCNT is initialized to H'0000 by a reset.
Rev. 6.00 Mar. 24, 2006 Page 170 of 412
REJ09B0142-0600