HD64F3664FPV Datasheet, PDF (190/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 Timer W
Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer
W.
Table 12.1 Timer W Functions
Item
Count clock
General registers
(output compare/input
capture registers)
Counter clearing function
Initial output value
setting function
Buffer function
Compare
0
match output ₁
Toggle
Input capture function
PWM mode
Interrupt sources
Input/Output Pins
Counter FTIOA
FTIOB
FTIOC
FTIOD
Internal clocks: φ, φ/2, φ/4, φ/8
External clock: FTCI
Period
GRA
specified in
GRA
GRB
GRC (buffer GRD (buffer
register for register for
GRA in
GRB in
buffer mode) buffer mode)
GRA
GRA
—
—
—
compare compare
match
match
—
Yes
Yes
Yes
Yes
—
—
—
—
—
—
Overflow
Yes
Yes
Yes
Yes
Yes
—
Compare
match/input
capture
Yes
Yes
Yes
Yes
Yes
Yes
Compare
match/input
capture
—
Yes
Yes
Yes
Yes
Yes
Compare
match/input
capture
—
Yes
Yes
Yes
Yes
Yes
Compare
match/input
capture
Rev. 6.00 Mar. 24, 2006 Page 160 of 412
REJ09B0142-0600