HD64F3664FPV Datasheet, PDF (179/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Timer V
Initial
Bit
Bit Name Value R/W Description
4
CCLR1 0
R/W Counter Clear 1 and 0
3
CCLR0 0
R/W These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on
TRGE in TCRV1.
2
CKS2
0
R/W Clock Select 2 to 0
1
CKS1
0
0
CKS0
0
R/W These bits select clock signals to input to TCNTV and
R/W ^{the counting condition in combination with ICKS0 in}
TCRV1.
Refer to table 11.2.
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
Bit 2
CKS2
0
1
TCRV0
Bit 1
CKS1
0
Bit 0
CKS0
0
1
1
0
1
0
0
1
1
0
1
TCRV1
Bit 0
ICKS0

0
1
0
1
0
1




Description
Clock input prohibited
Internal clock: counts on φ/4, falling edge
Internal clock: counts on φ/8, falling edge
Internal clock: counts on φ/16, falling edge
Internal clock: counts on φ/32, falling edge
Internal clock: counts on φ/64, falling edge
Internal clock: counts on φ/128, falling edge
Clock input prohibited
External clock: counts on rising edge
External clock: counts on falling edge
External clock: counts on rising and falling
edge
Rev. 6.00 Mar. 24, 2006 Page 149 of 412
REJ09B0142-0600