HD64F3664FPV Datasheet, PDF (275/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
Initial
Bit
Bit Name Value R/W Description
0
SCP
1
W Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop conditions
in master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
15.3.6 I²C Bus Status Register (ICSR)
The I²C bus status register (ICSR) consists of status flags. Also see table 15.4.
Initial
Bit
Bit Name Value R/W Description
7
ESTP
0
R/W Error Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag is cleared to 0
6
STOP
0
R/W Normal Stop Condition Detection Flag
This bit is valid in I²C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
• When 0 is written in STOP after reading STOP = 1
• When the IRIC flag is cleared to 0
Rev. 6.00 Mar. 24, 2006 Page 245 of 412
REJ09B0142-0600