HD64F3664FPV Datasheet, PDF (313/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 16.3 A/D Conversion Time (Single Mode)
Item
Symbol
Min
A/D conversion start delay t
6
D
Input sampling time
t_SPL
—
A/D conversion time
t
131
CONV
Note: All values represent the number of states.
CKS = 0
Typ Max
—
9
31
—
—
134
Section 16 A/D Converter
CKS = 1
Min Typ Max
4
—
5
—
15
—
69
—
70
16.4.4 External Trigger Input Timing
The A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1
in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG
input pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both
single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure
16.3 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
Rev. 6.00 Mar. 24, 2006 Page 283 of 412
REJ09B0142-0600