HD64F3664FPV Datasheet, PDF (230/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Serial Communication Interface 3 (SCI3)
14.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
14.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source.
Initial
Bit
Bit Name Value R/W Description
7
COM
0
R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5
PE
0
R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception.
4
PM
0
R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Rev. 6.00 Mar. 24, 2006 Page 200 of 412
REJ09B0142-0600