HD64F3664FPV Datasheet, PDF (286/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
Start condition issuance
SCL
(master output)
1
2
3
4
5
6
7
8
9
SCL
(slave output)
High
SDA
(master output)
SDA
(slave output)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [4]
A
RDRF
1
2
Bit 7 Bit 6
Data 1
IRIC
ICDRS
ICDRR
Interrupt
request
generation
Address + R/W
Address + R/W
User processing
[5] ICDR read [5] IRIC clearance
Figure 15.7 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0)
Rev. 6.00 Mar. 24, 2006 Page 256 of 412
REJ09B0142-0600