HD64F3664FPV Datasheet, PDF (293/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
Master receive operation
Set TRS = 0 in ICCR
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
Read ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Last receive?
Yes
No
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Read ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Last receive?
Yes
No
Clear IRIC in ICCR
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read. After reading
ICDR, please clear IRIC immediately.
[3] Wait for 1 byte to be received.
[4] Clear IRIC.
(to end the wait insertion)
[5] Wait for 1 byte to be received.
[6] Read the receive data.
[7] Clear IRIC.
[8] Wait for the next data to be
received.
[9] Clear IRIC.
(to end the wait insertion)
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
Yes
Set Wait = 0 in ICMR
Read ICDR
Clear IRIC in ICCR
Write BBSY = 0 and
SCP = 0 in ICCR
End
[10] Set acknowledge data for
the last reception.
[11] Clear IRIC.
(to end the wait insertion)
[12] Wait for 1 byte to be received.
[13] Clear wait mode.
Read receive data.
Clear IRIC.
(Note: After setting WAIT = 0,
IRIC should be cleared to 0.)
[14] Stop condition issuance.
Figure 15.14 Sample Flowchart for Master Receive Mode
Rev. 6.00 Mar. 24, 2006 Page 263 of 412
REJ09B0142-0600