HD64F3664FPV Datasheet, PDF (434/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
6.1.1 System Control Register 1
(SYSCR1)
Page Revision (See Manual for Details)
85 Amended
Bit Bit Name Description
3 NESEL Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ ) and the system clock pulse
W
generator generates the oscillator clock (φ ). This
OSC
bit selects the sampling frequency of the oscillator
clock when the watch clock signal (φ ) is sampled.
W
When φ = 4 to 16 MHz, clear NESEL to 0.
OSC
0: Sampling rate is φ_OSC/16
1: Sampling rate is φ /4
OSC
Table 7.2 Boot Mode Operation 102 Amended
Host Operation
Processing Contents
Communication Contents
LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 ^{. . .} H'00
H'00
H'55
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
H'55 reception.
9.5.3 Pin Functions
• P84/FTIOD Pin
136
Amended
Register
TMRW
TIOR1
PCR8
Bit Name
PWMD IOD2 IOD1 IOD0 PCR84 Pin Function
Setting Value 0
0
0
0
0
P84 input/FTIOD input pin
1
P84 output/FTIOD input pin
0
0
1
X
FTIOD output pin
0
1
X
X
FTIOD output pin
1
X
X
0
P84 input/FTIOD input pin
1
P84 output/FTIOD input pin
1
X
X
X
X
PWM output pin
Rev. 6.00 Mar. 24, 2006 Page 404 of 412
REJ09B0142-0600