HD64F3664FPV Datasheet, PDF (284/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
9. Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock
and drives SDA at the 9th receive clock pulse to return an ackowledge signal. Data can be
received continuously by repeating the step [5] to [9].
10. Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit in
ICCR to 1 to switch from receive mode to transmit mode.
11. Clear IRIC flag to 0 to release from the Wait State.
12. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
13. Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the IRIC
flag to 0. Clearing of the IRIC flag should be after the WAIT = 0. If the WAIT bit is cleared to
0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition cannot be issued because the output level of the SDA line is fixed as low.
14. Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Master tansmit mode Master receive mode
SCL
(master output) 9
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
1 23 4 56 78
9 1 23 4 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
[5]
Data 2
A
Data 1
User processing [1] TRS cleared to 0 [2] ICDR read [2] IRIC clearance
WAIT set to 1
(dummy read)
ACKB cleared to 0
[4] IRIC clearance [6] ICDR read [7] IRIC clearance
(Data 1)
Figure 15.6 Master Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, WAIT = 1)
Rev. 6.00 Mar. 24, 2006 Page 254 of 412
REJ09B0142-0600