HD64F3664FPV Datasheet, PDF (285/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
SCL
(master output)
8
9
1
2
3
4
5
6
7
8
9
1
2
SDA
Bit 0
(slave output)
SDA
Data 2 _[8]
(master output)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5]
A
Data 3
[8]
A
Bit 7 Bit 6
[5]
Data 4
IRIC
IRTR
ICDR
Data 1
Data 2
Data 3
User processing
[9] IRIC clearance [6] ICDR read
(Data 2)
[7] IRIC clearance
[6] ICDR read
(Data 3)
[9] IRIC clearance
[7] IRIC clearance
Figure 15.6 Master Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, WAIT = 1)
15.4.4 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1.
3. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1 and ninth clock is received for the following data receival, the slave device
drives SCL low from the falling edge of the receive clock until data is read into ICDR.
Rev. 6.00 Mar. 24, 2006 Page 255 of 412
REJ09B0142-0600