HD64F3664FPV Datasheet, PDF (116/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Initial
Bit
Bit Name Value
7
SMSEL
0
6
LSON
0
5
DTON
0
4
MA2
0
3
MA1
0
2
MA0
0
1
SA1
0
0
SA0
0
[Legend]
X: Don't care.
R/W Description
R/W Sleep Mode Selection
R/W Low Speed on Flag
R/W Direct Transfer on Flag
These bits select the mode to transit after the execution
of a SLEEP instruction, as well as bit SSBY of
SYSCR1.
For details, see table 6.2.
R/W Active Mode Clock Select 2 to 0
R/W These bits select the operating clock frequency in
R/W ^{active and sleep modes. The operating clock frequency}
changes to the set frequency after the SLEEP
instruction is executed.
R/W
0XX: φ
OSC
100: φ_OSC/8
101: φ /16
OSC
110: φ /32
OSC
111: φ_OSC/64
Subactive Mode Clock Select 1 and 0
R/W These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the
SLEEP instruction is executed.
00: φ /8
W
01: φ /4
W
1X: φ_W/2
Rev. 6.00 Mar. 24, 2006 Page 86 of 412
REJ09B0142-0600