HD64F3664FPV Datasheet, PDF (274/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
Initial
Bit
Bit Name Value R/W Description
1
IRIC
0
R/W I²C Bus Interface Interrupt Request Flag
Also see table 15.4.
[Setting conditions]
In master mode with I²C bus format
• When a start condition is detected in the bus line
state after a start condition is issued
• When a wait is inserted between the data and
acknowledge bit when WAIT = 1
• At the rising edge of the ninth transfer/receive clock,
and at the falling edge of the eighth transfer/receive
clock when a wait is inseted
• When a slave address is received after bus
arbitration is lost (when the AL flag is set to1)
• When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
I²C bus format slave mode
• When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (FS = 0 and when the TDRE or RDRF flag
is set to 1)
• When the general call address is detected (when
the ADZ flag is set to 1) and at the end of data
transfer up to the subsequent retransmission start
condition or stop condition detection (when the
TDRE or RDRF flag is set to 1)
• When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
• When a stop condition is detected (when the STOP
or ESTP flag is set to 1)
Clocked synchronous serial format
• At the end of data transfer (when the TDRE or
RDRF flag is set to 1)
• When a start condition is detected with serial format
selected
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
Rev. 6.00 Mar. 24, 2006 Page 244 of 412
REJ09B0142-0600