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HD64F3664FPV Datasheet, PDF (107/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The
subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1
OSC2
System
clock
oscillator
ÏOSC
(fOSC)
Duty
correction
circuit
ÏOSC
(fOSC)
System clock pulse generator
System
clock
divider
ÏOSC
ÏOSC/8
ÏOSC/16
ÏOSC/32
ÏOSC/64
Ï
Prescaler S
(13 bits)
Ï/2
to
Ï/8192
Subclock
X1
oscillator
ÏW
X2
(fW)
Subclock pulse generator
Subclock
divider
ÏW/2
ÏW/4
ÏW/8
ÏSUB
Prescaler W
(5 bits)
ÏW/8
to
ÏW/128
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are Ï and ÏSUB. The
system clock is divided by prescaler S to become a clock signal from Ï/8192 to Ï/2, and the
subclock is divided by prescaler W to become a clock signal from Ïw/128 to Ïw/8. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
Rev. 6.00 Mar. 24, 2006 Page 77 of 412
REJ09B0142-0600
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