HD64F3664FPV Datasheet, PDF (12/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

3.2.4 Interrupt Flag Register 1 (IRR1)......................................................................... 56
3.2.5 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57
3.3 Reset Exception Handling .................................................................................................. 59
3.4 Interrupt Exception Handling ............................................................................................. 59
3.4.1 External Interrupts .............................................................................................. 59
3.4.2 Internal Interrupts ............................................................................................... 61
3.4.3 Interrupt Handling Sequence ..................................................................... 61
3.4.4 Interrupt Response Time..................................................................................... 62
3.5 Usage Notes ........................................................................................................................ 64
3.5.1 Interrupts after Reset........................................................................................... 64
3.5.2 Notes on Stack Area Use .................................................................................... 64
3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 64
Section 4 Address Break ..................................................................................... 67
4.1 Register Descriptions.......................................................................................................... 68
4.1.1 Address Break Control Register (ABRKCR) ..................................................... 68
4.1.2 Address Break Status Register (ABRKSR) ........................................................ 70
4.1.3 Break Address Registers (BARH, BARL).......................................................... 70
4.1.4 Break Data Registers (BDRH, BDRL) ............................................................... 70
4.2 Operation ............................................................................................................................ 71
4.3 Usage Notes ........................................................................................................................ 73
Section 5 Clock Pulse Generators ....................................................................... 77
5.1 System Clock Generator ..................................................................................................... 78
5.1.1 Connecting Crystal Resonator ............................................................................ 78
5.1.2 Connecting Ceramic Resonator .......................................................................... 79
5.1.3 External Clock Input Method.............................................................................. 79
5.2 Subclock Generator ............................................................................................................ 80
5.2.1 Connecting 32.768-kHz Crystal Resonator ........................................................ 80
5.2.2 Pin Connection when Not Using Subclock......................................................... 81
5.3 Prescalers ............................................................................................................................ 81
5.3.1 Prescaler S .......................................................................................................... 81
5.3.2 Prescaler W......................................................................................................... 81
5.4 Usage Notes ........................................................................................................................ 82
5.4.1 Note on Resonators............................................................................................. 82
5.4.2 Notes on Board Design ....................................................................................... 82
Section 6 Power-Down Modes............................................................................ 83
6.1 Register Descriptions.......................................................................................................... 84
6.1.1 System Control Register 1 (SYSCR1) ................................................................ 84
Rev. 6.00 Mar. 24, 2006 Page x of xxviii