HD64F3664FPV Datasheet, PDF (291/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
15.4.8 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Sampling
clock
System clock
period
Figure 15.12 Block Diagram of Noise Canceler
Internal
SCL or
SDA
signal
Rev. 6.00 Mar. 24, 2006 Page 261 of 412
REJ09B0142-0600