HD64F3664FPV Datasheet, PDF (264/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
Figure 15.1 shows a block diagram of the I²C bus interface.
Figure 15.2 shows an example of I/O pin connections to external circuits. The I/O pins are NMOS
open drains. Set the upper limit of voltage applied to the power supply (V_CC) voltage range +
0.3 V, i.e. 5.8 V.
φ
PS
SCL
Noise
canceler
SDA
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address
comparator
SAR, SARX
[Legend]
ICCR: I²C bus control register
ICMR: I²C bus mode register
ICSR: I²C bus status register
ICDR: I²C bus data register
SAR: Slave address register
SARX: Slave address register X
PS: Prescaler
Interrupt
generator
Figure 15.1 Block Diagram of I²C Bus Interface
Interrupt
request
Rev. 6.00 Mar. 24, 2006 Page 234 of 412
REJ09B0142-0600