HD64F3664FPV Datasheet, PDF (310/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 A/D Converter
Initial
Bit
Bit Name Value R/W Description
2
CH2
0
R/W Channel Select 0 to 2
1
CH1
0
R/W Select analog input channels.
0
CH0
0
R/W When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 to AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
100: AN4
100: AN4
101: AN5
101: AN4 to AN5
110: AN6
110: AN4 to AN6
111: AN7
111: AN4 to AN7
AN4, AN5, AN6, and AN7 do not exist in the 42-pin
version.
16.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Initial
Bit
Bit Name Value
7
TRGE
0
6 to 1 —
All 1
0
—
0
R/W Description
R/W Trigger Enable
A/D conversion is started at the falling edge and the
rising edge of the external trigger signal (ADTRG)
when this bit is set to 1.
The selection between the falling edge and rising edge
of the external trigger pin (ADTRG) conforms to the
WPEG5 bit in the interrupt edge select register 2
(IEGR2).
—
Reserved
These bits are always read as 1.
R/W Reserved
Do not set this bit to 1, though the bit is
readable/writable.
Rev. 6.00 Mar. 24, 2006 Page 280 of 412
REJ09B0142-0600