HD64F3664FPV Datasheet, PDF (79/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7
and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent
this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the
bit in the work area, then write this data to PDR5.
Prior to executing BCLR
MOV.B
MOV.B
MOV.B
#3F, R0L
R0L, @RAM0
R0L, @PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
0
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
1
P54
Output
Low
level
1
0
1
P53
Output
Low
level
1
0
1
P52
Output
Low
level
1
0
1
P51
Output
Low
level
1
0
1
P50
Output
Low
level
1
0
1
BCLR instruction executed
BCLR #0, @RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
After executing BCLR
MOV.B @RAM0, R0L
MOV.B R0L, @PCR5
The work area (RAM0) value is written to PCR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
0
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
1
P54
Output
Low
level
1
0
1
P53
Output
Low
level
1
0
1
P52
Output
Low
level
1
0
1
P51
Output
Low
level
1
0
1
P50
Output
High
level
0
0
0
Rev. 6.00 Mar. 24, 2006 Page 49 of 412
REJ09B0142-0600