HD64F3664FPV Datasheet, PDF (269/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 I²C Bus Interface (IIC)
Table 15.2 Communication Format
SAR
FS
0
0
1
1
SARX
FSX
0
1
0
1
I²C Transfer Format
SAR and SARX are used as the slave addresses with the I²C bus
format.
Only SAR is used as the slave address with the I²C bus format.
Only SARX is used as the slave address with the I²C bus format.
Clock synchronous serial format (SAR and SARX are invalid)
15.3.4 I²C Bus Mode Register (ICMR)
The I²C bus mode register (ICMR) sets the transfer format and transfer rate. It can only be
accessed when the ICE bit in ICCR is 1.
Initial
Bit
Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
6
WAIT
0
R/W Wait Insertion Bit
This bit is valid only in master mode with the I²C bus
format.
When WAIT is set to 1, after the fall of the clock for the
final data bit, the IRIC flag is set to 1 in ICCR, and a
wait state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0,
data and acknowledge bits are transferred
consecutively with no wait inserted. The IRIC flag in
ICCR is set to 1 on completion of the acknowledge bit
transfer, regardless of the WAIT setting.
5
CKS2
0
R/W Serial Clock Select 2 to 0
4
CKS1
0
R/W This bit is valid only in master mode.
3
CKS0
0
R/W These bits select the required transfer rate, together
with the IICX bit in TSCR. Refer table 15.3.
Rev. 6.00 Mar. 24, 2006 Page 239 of 412
REJ09B0142-0600