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Section 15 I²C Bus Interface (IIC)
15.4.2 Master Transmit Operation
When data is set to ICDR during the period between the execution of an instruction to issue a start
condition and the creation of the start condition, the data may not be output normally, because
there will be a contention between a generation of a start condition and an output of data.
Although data H'FF is to be sent to the ICDR register by a dummy write operation before an issue
of a stop condition, the H'FF data may be output by the dummy write operation if the execution of
the instruction to issue a stop condition is delayed. To prevent these problems, follow the
flowchart shown below during the master transmit operation.
In I²C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations synchronize with the ICDR writing are described below.
1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in TSCR, according to the operating mode.
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and
generates the start condition.
5. Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt
request is sent to the CPU.
6. Write the data (slave address + R/W) to ICDR. With the I²C bus format (when the FS bit in
SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates
the 7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and
so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC continuously not to execute
other interrupt handling routine. If one frame of data has been transmitted before the IRIC
clearing, it can not be determine the end of transmission. The master device sequentially sends
the transmission clock and the data written to ICDR using the timing shown in figure 15.5. The
selected slave device (i.e. the slave device with the matching slave address) drives SDA low at
the 9th transmit clock pulse and returns an acknowledge signal.
7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has
not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the
transmit operation.
Rev. 6.00 Mar. 24, 2006 Page 251 of 412
REJ09B0142-0600