HD64F3664FPV Datasheet, PDF (76/446 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
Prior to executing BSET
Input/output
Pin state
PCR5
PDR5
P57
Input
Low
level
0
1
P56
Input
High
level
0
0
P55
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
Low
level
1
0
BSET instruction executed
BSET #0, @PDR5
The BSET instruction is executed for port 5.
After executing BSET
Input/output
Pin state
PCR5
PDR5
P57
Input
Low
level
0
0
P56
Input
High
level
0
1
P55
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
High
level
1
1
Description on operation
When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
Rev. 6.00 Mar. 24, 2006 Page 46 of 412
REJ09B0142-0600