PIC18F87K90 Datasheet, PDF (99/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
FB0h T3GCON
TMR3GE T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1 T3GSS0 0000 0x00
FB1h
FB2h
T3CON
TMR3L
TMR3CS1 TMR3CS0 T3CKPS1
Timer3 Register Low Byte
T3CKPS0
SOSCEN
T3SYNC
RD16
TMR3ON 0000 0000
xxxx xxxx
FB3h TMR3H
Timer3 Register High Byte
xxxx xxxx
FB4h CMSTAT
CMP3OUT CMP2OUT CMP1OUT
—
—
—
—
—
111- ----
FB5h
FB6h
FB7h
FB8h
FB9h
FBAh
FBBh
CVRCON
PIE4
PIR4
IPR4
PIE5
PIR5
CCP1CON
CVREN
CCP10IE⁽³⁾
CCP10IF⁽³⁾
CCP10IP⁽³⁾
TMR7GIE⁽³⁾
TMR7GIF⁽³⁾
CVROE
CCP9IE⁽³⁾
CCP9IF⁽³⁾
CCP9IP⁽³⁾
TMR12IE⁽³⁾
TMR12IF⁽³⁾
CVRSS
CCP8IE
CCP8IF
CCP8IP
TMR10IE⁽³⁾
TMR10IF⁽³⁾
P1M1
P1M0
DC1B1
CVR4
CCP7IE⁽³⁾
CCP7IF⁽³⁾
CCP7IP⁽³⁾
TMR8IE
TMR8IF
DC1B0
CVR3
CCP6IE
CCP6IF
CCP6IP
TMR7IE⁽³⁾
TMR7IF⁽³⁾
CCP1M3
CVR2
CCP5IE
CCP5IF
CCP5IP
TMR6IE
TMR6IF
CCP1M2
CVR1
CCP4IE
CCP4IF
CCP4IP
TMR5IE
TMR5IF
CCP1M1
CVR0
CCP3IE
CCP3IF
CCP3IP
TMR4IE
TMR4IF
CCP1M0
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
FBCh
FBDh
CCPR1L
CCPR1H
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
xxxx xxxx
FBEh ECCP1DEL
P1RSEN P1DC6
P1DC5
P1DC4
P1DC3
P1DC2
P1DC1
P1DC0 0000 0000
FBFh ECCP1AS
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000
FC0h ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0—00 0000
FC1h ADCON1
TRIGSEL1 TRIGSEL0 VCFG1
VCFG0
VNCFG
CHSN2
CHSN1
CHSN0 0000 0000
FC2h ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON -000 0000
FC3h ADRESL
A/D Result Register Low Byte
xxxx xxxx
FC4h
FC5h
ADRESH
SSP1CON2
A/D Result Register High Byte
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
xxxx xxxx
0000 0000
FC6h SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000
FC7h
FC8h
SSP1STAT
SSP1ADD
SMP
CKE
D/A
P
S
R/W
UA
BF
MSSP Address Register in I²C™ Slave Mode. SSP1 Baud Rate Reload Register in I²C Master Mode
0000 0000
0000 0000
FC9h
FCAh
SSP1BUF
T2CON
MSSP Receive Buffer/Transmit Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
T2CKPS1
xxxx xxxx
T2CKPS0 —000 0000
FCBh
FCCh
PR2
TMR2
Timer2 Period Register
Timer2 Register
1111 1111
0000 0000
FCDh
FCEh
T1CON
TMR1L
TMR1CS1 TMR1CS0 T1CKPS1
Timer1 Register Low Byte
T1CKPS0
SOSCEN
T1SYNC
RD16
TMR1ON 0000 0000
xxxx xxxx
FCFh TMR1H
Timer1 Register High Byte
xxxx xxxx
FD0h RCON
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
0111 11qq
FD1h
FD2h
WDTCON
IPR5
REGSLP
—
ULPLVL SRETEN
TMR7GIP⁽³⁾ TMR12IP⁽³⁾ TMR10I⁽³⁾ P TMR8IP
—
TMR7IP⁽³⁾
ULPEN
TMR6IP
ULPSINK
TMR5IP
SWDTEN 0—x0 —000
TMR4IP 1111 1111
FD3h OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
HFIOFS
SCS1
SCS0 0110 q000
FD4h SPBRGH1
USART1 Baud Rate Generator High Byte
0000 0000
FD5h
FD6h
T0CON
TMR0L
TMR0ON T08BIT
Timer0 Register Low Byte
T0CS
T0SE
PSA
TOPS2
TOPS1
TOPS0
1111 1111
xxxx xxxx
FD7h TMR0H
Timer0 Register High Byte
0000 0000
FD8h STATUS
—
—
—
N
OV
Z
DC
C
----x xxxx
FD9h
FDAh
FSR2L
FSR2H
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
xxxx xxxx
---- xxxx
FDBh PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – ---- ----
value of FSR2 offset by W
FDCh
FDDh
PREINC2
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 pre--incremented (not a physical register) ---- ----
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ----
FDEh
Note
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK90).
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90).
---- ----
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 99