PIC18F87K90 Datasheet, PDF (561/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
Half-Bridge PWM Output .................................. 258, 265
High-Voltage Detect Operation (VDIRMAG = 1)....... 402
I²C Acknowledge Sequence ..................................... 340
I²C Bus Data ............................................................. 534
I²C Bus Start/Stop Bits.............................................. 533
I²C Master Mode (7 or 10-Bit Transmission) ............ 338
I²C Master Mode (7-Bit Reception)........................... 339
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001).............................................. 323
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 324
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 329
I²C Slave Mode (10-Bit Transmission)...................... 325
I²C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011).............................................. 321
I²C Slave Mode (7-Bit Reception, SEN = 0) ............. 320
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 328
I²C Slave Mode (7-Bit Transmission)........................ 322
I²C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) .......................... 330
I²C Stop Condition Receive or Transmit Mode ......... 340
LCD Interrupt Timing in Quarter
Duty Cycle Drive ............................................... 296
LCD Reference Ladder Power Mode Switching ....... 281
LCD Sleep Entry/Exit When SLPEN = 1 or
CS = 00............................................................. 297
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 401
MSSP I²C Bus Data.................................................. 535
MSSP I²C Bus Start/Stop Bits .................................. 535
PWM Auto-Shutdown with
Auto-Restart Enabled ....................................... 264
PWM Auto-Shutdown with Firmware Restart............ 264
PWM Direction Change ............................................ 261
PWM Direction Change at Near
100% Duty Cycle .............................................. 262
PWM Output ............................................................. 246
PWM Output (Active-High)........................................ 256
PWM Output (Active-Low) ........................................ 257
Repeated Start Condition.......................................... 336
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 524
Send Break Character Sequence ............................. 364
Slave Synchronization .............................................. 307
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................. 71
SPI Mode (Master Mode).......................................... 306
SPI Mode (Slave Mode, CKE = 0) ............................ 308
SPI Mode (Slave Mode, CKE = 1) ............................ 308
Steering Event at Beginning of Instruction
(STRSYNC = 1) ................................................ 268
Steering Event at End of Instruction
(STRSYNC = 0) ................................................ 268
Synchronous Master Transmission
(Through TXEN) ............................................... 366
Synchronous Reception (Master Mode, SREN) ....... 367
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1........................ 71
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2........................ 71
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) ............... 70
Timer Pulse Generation ............................................ 232
Timer0 and Timer1 External Clock ........................... 527
Timer1 Gate Count Enable Mode ............................. 192
Timer1 Gate Single Pulse Mode ............................... 194
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 195
Timer1 Gate Toggle Mode........................................ 193
Timer3/5/7 Gate Count Enable Mode....................... 204
Timer3/5/7 Gate Single Pulse Mode......................... 206
Timer3/5/7 Gate Single Pulse/Toggle
Combined Mode ............................................... 207
Timer3/5/7 Gate Toggle Mode.................................. 205
Transition for Entry to Idle Mode ................................ 57
Transition for Entry to SEC_RUN Mode ..................... 53
Transition for Entry to Sleep Mode ............................. 56
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 442
Transition for Wake from Idle to Run Mode................ 57
Transition for Wake from Sleep (HSPLL) ................... 56
Transition from RC_RUN Mode to
PRI_RUN Mode.................................................. 55
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 53
Transition to RC_RUN Mode...................................... 55
Type-A in 1/2 MUX, 1/2 Bias Drive........................... 286
Type-A in 1/2 MUX, 1/3 Bias Drive........................... 288
Type-A in 1/3 MUX, 1/2 Bias Drive........................... 290
Type-A in 1/3 MUX, 1/3 Bias Drive........................... 292
Type-A in 1/4 MUX, 1/3 Bias Drive........................... 294
Type-A/Type-B in Static Drive .................................. 285
Type-B in 1/2 MUX, 1/2 Bias Drive........................... 287
Type-B in 1/2 MUX, 1/3 Bias Drive........................... 289
Type-B in 1/3 MUX, 1/2 Bias Drive........................... 291
Type-B in 1/3 MUX, 1/3 Bias Drive........................... 293
Type-B in 1/4 MUX, 1/3 Bias Drive........................... 295
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements.................... 528
CLKO and I/O Requirements.................................... 523
EUSART/AUSART Synchronous Receive
Requirements ................................................... 537
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 537
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 529
Example SPI Mode Requirements
(Master Mode, CKE = 1)................................... 530
Example SPI Mode Requirements
(Slave Mode, CKE = 0)..................................... 531
Example SPI Slave Mode Requirements
(CKE = 1).......................................................... 532
External Clock Requirements ................................... 521
High/Low-Voltage Detect Characteristics ................. 526
I²C Bus Data Requirements (Slave Mode) ............... 534
I²C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 533
Internal RC Accuracy (INTOSC)............................... 522
MSSP I²C Bus Data Requirements .......................... 536
MSSP I²C Bus Start/Stop Bits Requirements........... 535
PLL Clock ................................................................. 522
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements......................................... 525
Timer0 and Timer1 External Clock
Requirements ................................................... 527
Ultra Low-Power Wake-up........................................ 537
Top-of-Stack (TOS) Access................................................ 85
TSTFSZ ............................................................................ 489
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Preliminary
DS39957B-page 561