PIC18F87K90 Datasheet, PDF (167/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
11.6 PORTE, TRISE and
LATE Registers
PORTE is a 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output. The RE7 pin is also
configurable for open-drain output when ECCP2 is
active on this pin. Open-drain configuration is selected
by setting the CCP2OD control bit (ODCON1<6>)
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PADCFG1<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
Pins, RE<6:3>, are multiplexed with the LCD common
drives. I/O port functions are available only on those
PORTE pins according to which commons are active.
The configuration is determined by the LMUX<1:0>
control bits (LCDCON<1:0>). The availability is
summarized in Table 11-9.
TABLE 11-9:
PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS⁽¹⁾
LCDCON
<1:0>
Active LCD
Commons
PORTE Pins
Available for I/O
00
01
10
11
Note 1:
COM0
RE6, RE5, RE4
COM0, COM1
RE6, RE5
COM0, COM1
RE6
and COM2
All (COM0
through COM3)
None
If the LCD bias voltages are generated
using the internal resistor ladder, the
LCDBIASx pins are also available as I/O
ports (RE0, RE1 and RE2).
Pins, RE2, RE1 and RE0, are multiplexed with the
functions of LCDBIAS3, LCDBIAS2 and LCDBIAS1.
When LCD bias generation is required (in any applica-
tion where the device is connected to an external LCD),
these pins cannot be used as digital I/O. These pins
can be used as digital I/O, however, when the internal
resistor ladder is used for bias generation.
PORTE is also multiplexed with Enhanced PWM
outputs, B and C for ECCP1 and ECCP3, and outputs,
B, C and D for ECCP2. For all devices, their default
assignments are on PORTE<6:0>. On 80-pin devices,
the multiplexing for the outputs of ECCP1 and ECCP3 is
controlled by the ECCPMX Configuration bit. Clearing
this bit reassigns the P1B/P1C and P3B/P3C outputs to
PORTH.
RE7 is multiplexed with the LCD segment drive
(SEG31) that is controlled by the LCDSE3<7> bit. I/O
port function is only available when the segment is dis-
abled. RE7 can also be configured as the alternate
peripheral pin for the ECCP2 module. This is done by
clearing the CCP2MX Configuration bit.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further details,
refer to Section 3.7 “Reference Clock Output”.
EXAMPLE 11-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 167