PIC18F87K90 Datasheet, PDF (47/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
FIGURE 3-7:
PLL BLOCK DIAGRAM
PLLCFG (CONFIG1H<4>)
PLL Enable (OSCTUNE)
OSC2
HS or EC
OSC1 Mode
FIN
FOUT
Phase
Comparator
Loop
Filter
4
VCO
SYSCLK
3.5.2.2 PLL and HF-INTOSC
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
Section 3.6.2 “INTPLL Modes”. Care should be taken
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 4 MHz, 8 MHz or 16 MHz.
3.6 Internal Oscillator Block
The PIC18F87K90 family of devices includes an
internal oscillator block which generates two different
clock signals. Either clock can be used as the micro-
controller’s clock source, which may eliminate the need
for an external oscillator circuit on the OSC1 and/or
OSC2 pins.
The internal oscillator consists of three blocks, depend-
ing on the frequency of operation. They are
HF-INTOSC, MF-INTOSC and LF-INTRC.
In HF-INTOSC mode, the internal oscillator can provide
a frequency, ranging from 31 KHz to 16 MHz, with the
postscaler deciding the selected frequency
(IRCF<2:0>).
The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit
(OSCCON2<0>) also decide which INTOSC provides
the lower frequency (500 kHz to 31 KHz). For the
HF-INTOSC to provide these frequencies, INTSRC = 1
and MFI0SEL = 0.
In HF-INTOSC, the postscaler (IRCF<2:0>) provides the
frequency range of 31 kHz to 16 MHz. If HF-INTOSC is
used with the PLL, the input frequency to the PLL should
be 4 MHz to 16 MHz (IRCF<2:0> = 111, 110 or 101).
For MF-INTOSC mode to provide a frequency range of
500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1.
The postscaler (IRCF<2:0>), in this mode, provides the
frequency range of 31 kHz to 500 kHz.
The LF-INTRC can provide only 31 kHz if INTSRC = 0.
The LF-INTRC provides 31 kHz and is enabled if it is
selected as the device clock source. The mode is
enabled automatically when any of the following is
enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 28.0 “Special Features of the CPU”.
The clock source frequency (HF-INTOSC, MF-INTOSC
or LF-INTRC direct) is selected by configuring the IRCF
bits of the OSCCON register, as well the INTSRC and
MFIOSEL bits. The default frequency on device Resets
is 8 MHz.
3.6.1 INTIO MODES
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
OSC Configuration bits, are available:
• In INTIO1 mode, the OSC2 pin (RA6) outputs
FOSC/4, while OSC1 functions as RA7 (see
Figure 3-8) for digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-9). Both
are available as digital input and output ports.
FIGURE 3-8: INTIO1 OSCILLATOR MODE
RA7
FOSC/4
I/O (OSC1)
PIC18F87K90
OSC2
FIGURE 3-9: INTIO2 OSCILLATOR MODE
RA7
I/O (OSC1)
PIC18F87K90
RA6
I/O (OSC2)
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 47