PIC18F87K90 Datasheet, PDF (421/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
27.9 Operation During Sleep/Idle Modes
27.9.1 SLEEP MODE
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
27.9.2 IDLE MODE
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
27.10 Effects of a Reset on CTMU
Upon Reset, all registers of the CTMU are cleared. This
disables the CTMU module, turns off its current source
and returns all configuration options to their default set-
tings. The module needs to be re-initialized following
any Reset.
If the CTMU is in the process of taking a measurement at
the time of Reset, the measurement will be lost. A partial
charge may exist on the circuit that was being measured,
which should be properly discharged before the CTMU
makes subsequent attempts to make a measurement.
The circuit is discharged by setting and clearing the
IDISSEN bit (CTMUCONH<1>) while the A/D Converter
is connected to the appropriate channel.
TABLE 27-1: REGISTERS ASSOCIATED WITH CTMU MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
CTMUCONH CTMUEN
—
CTMUSIDL TGEN
EDGEN EDGSEQEN IDISSEN CTTRIG
78
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 78
CTMUICON ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
78
PIR3
TMR5GIF LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF CCP1IF RTCCIF
75
PIE3
TMR5GIE LCDIE
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE RTCCIE
75
IPR3
TMR5GIP LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP RTCCIP
75
Legend: — = unimplemented, read as ‘0’
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 421