PIC18F87K90 Datasheet, PDF (284/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
20.7 LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
TABLE 20-5: FRAME FREQUENCY
FORMULAS
Multiplex
Frame Frequency =
Static
1/2
1/3
1/4
Note:
Clock Source/(4 x 1 x (LP<3:0> + 1))
Clock Source/(2 x 2 x (LP<3:0> + 1))
Clock Source/(1 x 3 x (LP<3:0> + 1))
Clock Source/(1 x 4 x (LP<3:0> + 1))
Clock source is (FOSC/4)/8192,
Timer1 Osc/32 or INTRC/32.
TABLE 20-6:
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC AT 32 MHz, TIMER1 AT
32.768 kHz OR INTRC OSC
LP<3:0> Static
1/2
1/3
1/4
1
125
125
167
125
2
83
83
111
83
3
62
62
83
62
4
50
50
67
50
5
42
42
56
42
6
36
36
48
36
7
31
31
42
31
20.8 LCD Waveform Generation
LCD waveform generation is based on the philosophy
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC
component and can take only one of the two rms values.
The higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveforms:
Type-A and Type-B. In a Type-A waveform, the phase
changes within each common type, whereas a Type-B
waveform’s phase changes on each frame boundary.
Thus, Type-A waveforms maintain 0 VDC over a single
frame, whereas Type-B waveforms take two frames.
Note 1:
If Sleep has to be executed with LCD Sleep
enabled (SLPEN (LCDCON<6>) = 1),
care must be taken to execute Sleep only
when VDC on all the pixels is ‘0’.
2: When the LCD clock source is (FOSC/4)/
8192, if Sleep is executed irrespective of
the LCDCON<SLPEN> setting, the LCD
goes into Sleep. Thus, take care to see
that VDC on all pixels is ‘0’ when Sleep is
executed.
Figure 20-7 through Figure 20-17 provide waveforms
for static, half-multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
DS39957B-page 284
Preliminary
 2010 Microchip Technology Inc.