PIC18F87K90 Datasheet, PDF (152/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
11.1.3 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the registers
ODCON1, ODCON2 and ODCON3.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 11-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
FIGURE 11-2:
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
3.3V
+5V
PIC18F67K90
VDD
TXX ^3.3V
5V
(at logic ‘1’)
REGISTER 11-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
SSP1OD
CCP2OD CCP1OD
—
—
—
—
bit 7
R/W-0
SSP2OD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-1
bit 0
SSP1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
CCP2OD: ECCP2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
CCP1OD: ECCP1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
Unimplemented: Read as ‘0’
SSP2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
DS39957B-page 152
Preliminary
 2010 Microchip Technology Inc.