PIC18F87K90 Datasheet, PDF (95/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
EF4h LCDCON
LCDEN
SLPEN
WERR
—
CS1
CS0
LMUX1
LMUX0 000- 0000
EF5h
EF6h
LCDPS
LCDSE0
WFT
SE07
BIASMD
SE06
LCDA
SE05
WA
SE04
LP3
SE03
LP2
SE02
LP1
SE01
LP0
SE00
0000 0000
0000 0000
EF7h
EF8h
LCDSE1
LCDSE2
SE15
SE23
SE14
SE22
SE13
SE21
SE12
SE20
SE11
SE19
SE10
SE18
SE09
SE17
SE08
SE16
0000 0000
0000 0000
EF9h
EFAh
EFBh
EFCh
LCDSE3
LCDSE4
LCDSE5⁽²⁾
LCDRL
SE31
SE39
SE47
LRLAP1
SE30
SE38
SE46
LRLAP0
SE29
S37
SE45
LRLBP1
SE28
SE36
SE44
LRLBP0
SE27
SE35
SE43
—
SE26
SE34
SE42
LRLAT2
SE25
SE33
SE41
LRLAT1
SE24
SE32
SE40
LRLAT0
0000 0000
0000 0000
0000 0000
0000 -000
EFDh
EFEh
LCDREF
SSP2CON2
LCDIRE
GCEN
LCDIRS LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE 0000 0000
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
EFFh SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000
F00h
F01h
SSP2STAT
SSP2ADD
SMP
CKE
D/A
P
S
R/W
UA
BF
MSSP Address Register in I²C™ Slave Mode. SSP1 Baud Rate Reload Register in I²C Master Mode
0000 0000
0000 0000
F02h
F03h
SSP2BUF
T4CON
MSSP Receive Buffer/Transmit Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON
T4CKPS1
xxxx xxxx
T4CKPS0 -000 0000
F04h PR4
Timer4 Period Register
0000 0000
F05h TMR4
Timer4 Register
1111 1111
F06h CCP7CON
—
—
DC7B1
DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000
F07h CCPR7L
Capture/Compare/PWM Register 7 Low Byte
xxxx xxxx
F08h CCPR7H
Capture/Compare/PWM Register7 High Byte
xxxx xxxx
F09h CCP6CON
—
—
DC6B1
DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000
F0Ah CCPR6L
Capture/Compare/PWM Register 6 Low Byte
xxxx xxxx
F0Bh
F0Ch
CCPR6H
CCP5CON
Capture/Compare/PWM Register6 High Byte
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
xxxx xxxx
CCP5M0 --00 0000
F0Dh
F0Eh
CCPR5L
CCPR5H
Capture/Compare/PWM Register 5 Low Byte
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx
xxxx xxxx
F0Fh
F10h
CCP4CON
CCPR4L
—
—
DC4B1
DC4B0
Capture/Compare/PWM Register 4 Low Byte
CCP4M3
CCP4M2
CCP4M1
CCP4M0 --00 0000
xxxx xxxx
F11h
F12h
CCPR4H
T5GCON
Capture/Compare/PWM Register 4 High Byte
TMR5GE T5GPOL T5GTM T5GSPM
T5GGO/
T5DONE
T5GVAL
T5GSS1
xxxx xxxx
T5GSS0 0000 0000
F13h T5CON
TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC
RD16
TMR5ON 0000 0000
F14h
F15h
F16h
F17h
TMR5L
TMR5H
PMD3
PMD2
Timer5 Register Low Byte
Timer5 Register High Byte
CCP10MD⁽³⁾ CCP9MD⁽³⁾ CCP8MD
TMR10MD⁽³⁾ TMR8MD TMR7MD⁽³⁾
CCP7MD
TMR6MD
CCP6MD
TMR5MD
CCP5MD
CMP3MD
0000 0000
CCP4MD
CMP2MD
xxxx xxxx
TMR12MD⁽³⁾ 0000 0000
CMP1MD 0000 0000
F18h
F19h
PMD1
PMD0
—
CCP3MD
CTMUMD
CCP2MD
RTCCMD TMR4MD TMR3MD TMR2MD
CCP1MD UART2MD UART1MD SSP2MD
TMR1MD
SSP1MD
—
ADCMD
-000 000-
0000 0000
F1Ah
F1Bh
PSTR3CON
PSTR2CON
CMPL1
CMPL1
CMPL0
CMPL0
—
STRSYNC STRD
—
STRSYNC STRD
STRC
STRC
STRB
STRB
STRA
STRA
00-0 0001
00-0 0001
F1Ch TXREG2
Transmit Data FIFO
xxxx xxxx
F1Dh RCREG2
Receive Data FIFO
0000 0000
F1Eh SPBRG2
USART2 Baud Rate Generator Low Byte
0000 0000
F1Fh SPBRGH2
USART2 Baud Rate Generator High Byte
0000 0000
F20h BAUDCON2
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN 0100 0-00
F21h TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010
F22h RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x
F23h
Note
ANCON2
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17
1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK90).
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90).
ANSEL16 1111 1111
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 95