PIC18F87K90 Datasheet, PDF (46/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows how the R/C combination is
connected.
FIGURE 3-3:
VDD
RC OSCILLATOR MODE
REXT
OSC1
Internal
Clock
CEXT
VSS
OSC2/CLKO
FOSC/4
PIC18FXXXX
Recommended values: 3 k  REXT  100 k
20 pF CEXT  300 pF
The RCIO Oscillator mode (Figure 3-4) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-4:
VDD
RCIO OSCILLATOR MODE
REXT
CEXT
VSS
RA6
OSC1
Internal
Clock
I/O (OSC2)
PIC18FXXXX
Recommended values: 3 k  REXT  100 k
20 pF CEXT  300 pF
3.5.1
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1/CLKI
PIC18F87K90
OSC2/CLKO
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-6. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-6:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
Open
OSC1
PIC18F87K90
(HS Mode)
OSC2
3.5.2 PLL FREQUENCY MULTIPLIER
A Phase Lock Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.5.2.1 HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to 64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
For the HF-INTOSC as primary, the PLL must be
enabled with the PLLEN. This provides software con-
trol for the PLL, enabling even if PLLCFG is set to ‘1’,
so that the PLL is enabled only when the HF-INTOSC
frequency is within the 4 MHz to 16 MHz input range.
This also enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HF-INTOSC mode only if the
input frequency is in the range of 4 MHz-16 MHz.
DS39957B-page 46
Preliminary
 2010 Microchip Technology Inc.