PIC18F87K90 Datasheet, PDF (394/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
24.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current.
To minimize power consumption while in Sleep mode,
turn off the comparators (CON = 0) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMxCON register are not affected.
24.8 Effects of a Reset
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
PIR6
—
—
—
EEIF
PIE6
—
—
—
EEIE
IPR6
—
—
—
EEIP
CM1CON
CON
COE
CPOL EVPOL1
CM2CON
CON
COE
CPOL EVPOL1
CM3CON
CON
COE
CPOL EVPOL1
CVRCON CVREN CVROE CVRSS CVR4
CMSTAT CMP3OUT CMP2OUT CMP1OUT —
PORTF
RF7
RF6
RF5
RF4
LATF
LATF7
LATF6 LATF5 LATF4
TRISF
TRISF7 TRISF6 TRISF5 TRISF4
PORTG
—
—
RG5
RG4
LATG
—
—
—
LATG4
TRISG
—
—
—
TRISG4
PORTH
RH7
RH6
RH5
RH4
LATH
LATH7
LATH6 LATH5 LATH4
TRISH
TRISH7 TRISH6 TRISH5 TRISH4
Legend: — = unimplemented, read as ‘0’.
RBIE
—
—
—
EVPOL0
EVPOL0
EVPOL0
CVR3
—
RF3
LATF3
TRISF3
RG3
LATG3
TRISG3
RH3
LATH3
TRISH3
TMR0IF
CMP3IF
CMP3IE
CMP3IP
CREF
CREF
CREF
CVR2
—
RF2
LATF2
TRISF2
RG2
LATG2
TRISG2
RH2
LATH2
TRISH2
INT0IF
CMP2IF
CMP2IE
CMP2IP
CCH1
CCH1
CCH1
CVR1
—
RF1
LATF1
TRISF1
RG1
LATG1
TRISG1
RH1
LATH1
TRISH1
Bit 0
Reset
Values on
Page:
RBIF
73
CMP1IF
75
CMP1IE
78
CMP1IP
75
CCH0
78
CCH0
79
CCH0
79
CVR0
75
—
75
—
76
—
76
—
76
RG0
76
LATG0
76
TRISG0
76
RH0
76
LATH0
76
TRISH0
76
DS39957B-page 394
Preliminary
 2010 Microchip Technology Inc.