PIC18F87K90 Datasheet, PDF (156/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 11-1: PORTA FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0/ULPWU
RA0
0
O
DIG LATA<0> data output; not affected by analog input.
1
I
TTL PORTA<0> data input; disabled when analog input enabled.
AN0
1
I
ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
ULPWU
1
I
ANA Ultra low-power wake-up input.
RA1/AN1/SEG18
RA1
0
O
DIG LATA<1> data output; not affected by analog input.
1
I
TTL PORTA<1> data input; disabled when analog input is enabled.
AN1
1
I
ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
SEG18
1
O ANA LCD Segment 18 output; disables all other pin functions.
RA2/AN2/VREF-
RA2
0
O
DIG LATA<2> data output; not affected by analog input.
1
I
TTL PORTA<2> data input; disabled when analog functions are enabled.
AN2
1
I
ANA A/D Input Channel 2. Default input configuration on POR.
VREF-
1
I
ANA A/D and comparator low reference voltage input.
RA3/AN3/VREF+
RA3
0
O
DIG LATA<3> data output; not affected by analog input.
1
I
TTL PORTA<3> data input; disabled when analog input is enabled.
AN3
1
I
ANA A/D Input Channel 3. Default input configuration on POR.
VREF+
1
I
ANA A/D and comparator high reference voltage input.
RA4/T0CKI/
SEG14
RA4
0
O
DIG LATA<4> data output.
1
I
ST PORTA<4> data input. Default configuration on POR.
T0CKI
x
I
ST Timer0 clock input.
SEG14
1
O ANA LCD Segment 14 output; disables all other pin functions.
RA5/AN4/SEG15/
RA5
T1CKI/T3G/
HLVDIN
AN4
0
O
DIG LATA<5> data output; not affected by analog input.
1
I
TTL PORTA<5> data input; disabled when analog input is enabled.
1
I
ANA A/D Input Channel 4. Default configuration on POR.
SEG15
1
O ANA LCD Segment 15 output; disables all other pin functions.
T1CKI
x
I
ST Timer1 clock input.
T3G
x
I
ST Timer3 external clock gate input.
HLVDIN
1
I
ANA High/Low-Voltage Detect external trip point input.
OSC2/CLKO/RA6
OSC2
x
O ANA Main oscillator feedback output connection (HS, XT and LP modes).
CLKO
x
O
DIG System cycle clock output (FOSC/4, EC and INTOSC modes).
RA6
0
O
DIG LATA<6> data output; disabled when OSC2 Configuration bit is set.
1
I
TTL PORTA<6> data input; disabled when OSC2 Configuration bit is set.
OSC1/CLKI/RA7
OSC1
x
I
ANA Main oscillator input connection (HS, XT and LP modes).
CLKI
x
I
ANA Main external clock source input (EC modes).
RA7
0
O
DIG LATA<7> data output; disabled when OSC2 Configuration bit is set.
1
I
TTL PORTA<7> data input; disabled when OSC2 Configuration bit is set.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39957B-page 156
Preliminary
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