PIC18F87K90 Datasheet, PDF (369/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
22.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
22.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
e) If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 22-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
73
PIR1
—
ADIF
RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF
75
PIE1
—
ADIE
RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE
75
IPR1
—
ADIP
RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP
75
PIR3
TMR5GIF LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
75
PIE3
TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
75
IPR3
TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
75
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
75
TXREG1 EUSART1 Transmit Register
75
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
75
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
77
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
74
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
75
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
79
TXREG2 EUSART2 Transmit Register
80
TXSTA2
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
79
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
79
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
80
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte
80
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 369