PIC18F87K90 Datasheet, PDF (98/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
F81h
F82h
F83h
F84h
F85h
F86h
F87h
F88h
F89h
F8Ah
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
F98h
F99h
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
FA1h
FA2h
FA3h
FA4h
FA5h
FA6h
FA7h
FA8h
FA9h
FAAh
FABh
FACh
FADh
FAEh
FAFh
Note
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
PORTF
PORTG
PORTH⁽²⁾
PORTJ⁽²⁾
RF7
—
RH7
RJ7
RF6
—
RH6
RJ6
RF5
RG5⁽¹⁾
RH5
RJ5
RF4
RG4
RH4
RJ4
RF3
RG3
RH3
RJ3
RF2
RG2
RH2
RJ2
RF1
RG1
RH1
RJ1
LATA
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATG
LATH⁽²⁾
LATJ⁽²⁾
—
LATH7
LATJ7
—
LATH6
LATJ6
—
LATH5
LATJ5
LATG4
LATH4
LATJ4
LATG3
LATH3
LATJ3
LATG2
LATH2
LATJ2
LATG1
LATH1
LATJ1
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISG
TRISH⁽²⁾
TRISJ⁽²⁾
—
TRISH7
TRISJ7
—
TRISH6
TRISJ6
—
TRISH5
TRISJ5
TRISG4
TRISH4
TRISJ4
TRISG3
TRISH3
TRISJ3
TRISG2
TRISH2
TRISJ2
TRISG1
TRISH1
TRISJ1
OSCTUNE
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
PSTR1CON
CMPL1
CMPL0
—
STRSYNC STRD
STRC
STRB
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE TMR1GIE TMR2IE
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF TMR1GIF TMR2IF
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP TMR1GIP TMR2IP
PIE2
OSCFIE
—
SSP2IE
BCL2IE
BCL1IE
HLVDIE
TMR3IE
PIR2
OSCFIF
—
SSP2IF
BCL2IF
BCL1IF
HLVDIF
TMR3IF
IPR2
OSCFIP
—
SSP2IP
BCL2IP
BCL1IP
HLVDIP
TMR3IP
PIE3
TMR5GIE LCDIE
RC2IE
TX2IE
CTMUIE CCP2IE CCP1IE
PIR3
TMR5GIF LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
IPR3
TMR5GIP LCDIP
RC2IP
TX2IP
CTMUIP CCP2IP CCP1IP
PIR6
—
—
—
EEIF
—
CMP3IF CMP2IF
—
—
—
—
—
—
—
—
HLVDCON
VDIRMAG BGVST
IRVST
HLVDEN HLVDL3 HLVDL2 HLVDL1
IPR6
—
—
—
EEIP
—
CMP3IP CMP2IP
T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TXREG1
USART1 Transmit Register
RCREG1
USART1 Receive Register
SPBRG1
USART1 Baud Rate Generator
1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK90).
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90).
RB0
RC0
RD0
RE0
—
RG0
RH0
RJ0
LATA0
LATB0
LATC0
LATD0
LATE0
—
LATG0
LATH0
LATJ0
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
—
TRISG0
TRISH0
TRISJ0
TUN0
STRA
TMR1IE
TMR1IF
TMR1IP
TMR3GIE
TMR3GIF
TMR3GIP
RTCCIE
RTCCIF
RTCCIP
CMP1IF
—
HLVDL0
CMP1IP
T1GSS0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxx-
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxx-
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 111-
---1 1111
1111 1111
1111 1111
0000 0000
00-0 0001
-000 0000
-000 0000
-111 1111
0-10 0000
0-10 0000
1-00 1110
0000 0000
0000 0000
1111 1111
---0 -000
---- ----
0000 0000
---1 -111
0000 0x00
RX9D
TX9D
0000 000x
0000 0010
xxxx xxxx
0000 0000
0000 0000
DS39957B-page 98
Preliminary
 2010 Microchip Technology Inc.