PIC18F87K90 Datasheet, PDF (174/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 11-14: PORTG FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG2/RX2/DT2/
AN18/C3INA
RG2
0
O
DIG LATG<2> data output.
1
I
ST PORTG<2> data input.
RX2
1
I
ST Asynchronous serial receive data input (EUSART module).
DT2
1
O
DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST Synchronous serial data input (EUSART module); user must configure
as an input.
AN18
1
I
ANA A/D Input Channel 18. Default input configuration on POR. Does not
affect digital output.
C3INA
x
I
ANA Comparator 3 Input A.
RG3/CCP4/AN17/
P3D/C3INB
RG3
0
O
DIG LATG<3> data output.
1
I
ST PORTG<3> data input.
CCP4
0
O
DIG CCP4 compare/PWM output. Takes priority over port data.
1
I
ST CCP4 capture input.
AN17
1
I
ANA A/D Input Channel 17. Default input configuration on PR. Does not
affect digital output.
C3INB
x
I
ANA Comparator 3 Input B.
P3D
0
O
— ECCP3 PWM Output D. May be configured for tri-state during
Enhanced PWM.
RG4/SEG26/
RG4
0
O
DIG LATG<4> data output.
RTCC/T7CKI/
1
I
ST PORTG<4> data input.
T5G/CCP5/
AN16/P1D/
SEG26
1
O
ANA LCD Segment 26 output; disables all other pin functions.
C3INC
RTCC
x
O
DIG RTCC output.
T7CKI
x
I
ST Timer7 clock input.
T5G
x
I
ST Timer5 external clock gate input.
CCP5
0
O
DIG CCP5 compare/PWM output. Takes priority over port data.
1
I
ST CCP5 capture input.
AN16
1
I
ANA A/D Input Channel 17. Default input configuration on POR. Does not
affect digital output.
C3INC
x
I
ANA Comparator 3 Input C.
P1D
0
O
— ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
RG5
I
ST See the MCLR/RG5 pin.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
PORTG
—
—
RG5⁽¹⁾
RG4
RG3
RG2
RG1
RG0
76
TRISG
—
—
—
TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
76
LCDSE3
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24
81
ANCON2
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 79
ODCON1
SSP1OD CCP2OD CCP1OD —
—
—
— SSP2OD 79
ODCON2
CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 79
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
DS39957B-page 174
Preliminary
 2010 Microchip Technology Inc.