PIC18F87K90 Datasheet, PDF (203/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
15.2 Timer3/5/7 Operation
Timer3, Timer5 and Timer7 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (FOSC/4). When TMRxCSx = 01, the
Timer3/5/7 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3/5/7 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
FIGURE 15-1:
TxGSS<1:0>
TIMER3/5/7 BLOCK DIAGRAM
TxG
00
TxGSPM
From TMR(x + 1)
Match PR(x + 1)
01
From Comp. 1
Output
10
From Comp. 2
11
Output
TxGPOL
TxG_IN
TMRxON
TxGTM
DQ
CK ^Q
R
Set Flag bit
TMRxIF on
Overflow
TMRx⁽²⁾
TMRxH
TMRxL
0
Single Pulse
1
Acq. Control
TxGGO/TxDONE
0
TxGVAL _{D Q}
1
Q1 EN
Interrupt
det
TMRxON
TMRxGE
EN
TxCLK
0
QD
Synchronized
Clock Input
1
SOSCO
SOSCI
SOSCEN
TxCKI
OUT
TxOSC
EN
(1)
TMRxCS<1:0>
TxSYNC
Prescaler
Synchronize⁽³⁾
1
1, 2, 4, 8
det
10
0
FOSC
2
TxCKPS<1:0>
Internal ⁰¹
Clock
FOSC/4
Internal ⁰⁰
FOSC/2
Internal
Clock
Sleep Input
Clock
Data Bus
RD
T3GCON
Set
TMRxGIF
Note 1:
2:
3:
ST Buffer is high-speed type when using TxCKI.
Timerx registers increment on rising edge.
Synchronize does not operate while in Sleep.
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 203